An arbiter is a well known interface circuit that controls a communication protocol on the basis of assigning priority to a particular input signal selected from a plurality of input signals in order to determine a processing sequence for the input signals. The priority assignment may be based on temporal aspects of the signals, e.g., the order of arrivals at the arbiter's inputs. Assigning a priority to the particular input signal is then to be understood as selecting the particular input signal on the basis of its temporal characteristics with respect to the temporal characteristics of the other input signals: e.g., the particular input signal is the first to have arrived and determines the further processing. Typically, arbiters are used for controlling the communication between transmitting stations and receiving stations interconnected via a bus system.
U.S. Pat. No. 4,835,422 issued to Dike et al. discusses an electronic arbiter circuit with an input section that provides relative priority signals upon receiving a plurality of input signals. Each respective relative priority signal specifies which one of a respective pair of input signals has gained priority over the other input signal. The relative priority signals associated with all pairs of input signals are supplied to a decode logic circuit. The decode logic circuit operates on the relative priority signals in order to furnish output signals specifying an absolute priority of a particular one of the input signals. That is, the output signals indicate which one of the input signals is considered to have gained priority over all other input signals.
In addition, the decode logic circuit takes care of priority conflicts that may occur at the level of the relative priority signals. A priority conflict is an event wherein, for example, three or more input signals arrive substantially simultaneously within the resolution of the electronics and the delay paths involved. Such an event gives rise to inconsistences. For example, the relative priority signals may indicate that the respective input signals at first, second and third input terminals respectively gained priority over the input signals at the second, third and first input terminals. Assuming that one of these input signals indeed was the first to arrive overall, such a cyclic relationship does not give an unambiguous absolute priority winner. The decode logic circuit is designed to resolve the conflict by selecting in a predetermined manner one of the input signals, which was involved in causing the conflict, as the absolute priority winner.
The design of the decode logic circuit for conventional arbiters rapidly becomes increasingly complicated when the number of input signals is raised. This is due, among other things, to the growing number of logic combinations of the input signals that should be taken into account when anticipating all priority conflicts possible.